The present invention relates to a communication control apparatus, a network, and a network system.
When LSI devices and the like are mutually connected, a high-speed serial bus is typically used due to limitations to a wiring length in a substrate, and PCI Express is widely used as an accepted standard. In PCI Express, a tree-structured network having one RC (Route Complex) as a base is usually constructed (e.g., Japanese Patent Application Laid-open No. 2005-332316).
When a plurality of PCI Express networks are connected, each network is connected to another network from an end point of the PCI Express network via an NTB (Non-Transparent Bridge).
However, since the NTB is an end point, there is a limitation that a configuration request cannot be issued because of a protocol of PCI Express. Consequently, for example, when two PCI Express networks are connected, the configuration request cannot be issued from a route complex of one of the networks to a device on the other network, and hence it is not possible to completely control the device on the other network.
When a plurality of PCI Express networks are connected, there are cases where mutual control is required. In general, a special message for requesting the execution of the request is sent to the route complex of the other network to generate the request by software. However, in such implementation, the intervention of a processor for controlling the route complex of the sending destination is essential. Accordingly, when the processor becomes unresponsive, there arises a problem that the route complex cannot be controlled from the sending source.
FIG. 9 illustrates a typical example in which PCI Express networks are connected by an NTB connection. In the NTB connection, a configuration request cannot be sent from a PCI Express bridge. Therefore, in the structure illustrated in FIG. 9, it is not possible to completely control an end device 85 on a board 71 side from a CPU 921 on a board 72 side. Similarly, it is not possible to completely control an end device 95 on the board 72 side from a CPU 821 on the board 71 side.